1. Field of the Invention
The present invention relates to semiconductor processing and, in particular, to a method of electroless and electrodeposition of near-noble metals with phosphorus or boron to form ultra-shallow junctions using a salicide as a diffusion source.
2. Description of the Related Art
The ever-present desire in the semiconductor industry for reduced costs and increased performance and yields has led to ever more highly integrated designs. In order to accommodate more devices on a given wafer, there is a corresponding drive to reduce device feature sizes. However, reducing feature size while maintaining predictable and stable device performance and satisfactory yields is a continuing challenge to semiconductor processes and materials. One difficulty found in MOS processing is achieving increasingly shallow source/drain junctions while maintaining predictable and desired device performance.
The source/drain junctions are formed in an NMOS device, for example, by creating two separate n-type regions in an underlying lightly doped p-type well. The junctions are defined as the places in the dopant gradient where the concentration of n and p types majority carriers are equal, i.e., where the material transitions from a p-type to an n-type. In an NMOS device, a gate region is placed between and adjacent the source and drain regions and insulated from the underlying substrate such that minimal current can flow through the gate terminal. The two n-type regions separated by the p-type well form two back-to-back pn junctions between the source and drain terminals and, ideally, current flow between the source and drain terminals is controlled by a voltage applied to the gate.
A positive voltage applied to the gate creates an electrostatic field in the p-type well under the gate insulator, which attracts electrons from the source and drain n-type regions. When a sufficiently high voltage, known as the threshold voltage, is applied to the gate, an inverted channel of electron carriers extends under the gate between the source and drain and thus a current between the source and drain will flow in response to a voltage applied between the source and drain. When the gate voltage is below the threshold voltage, the inverted channel should not extend between the source and drain and current flow between the source and drain is limited to reverse leakage currents. The leakage current needs to remain low so that an applied voltage between the source and drain does not result in a significant current flow absent an applied gate voltage. Otherwise, circuits employing the devices will not function as intended.
It can be appreciated from the geometry of a MOS device that smaller device sizes, in particular a shorter distance between the source and drain, i.e. a shorter gate, will allow the conducting channel between the source and drain to form more rapidly and allow the device to operate at higher switching speeds. As the device dimensions are reduced to achieve higher packing densities and improved performance, the junction depth needs to be scaled in proportion to the junction length.
An ultra-shallow junction is currently considered to be in the range of 600-700 xc3x85. Achieving an effective ultra-shallow source/drain junction is a great challenge using conventional implantation based MOS device fabrication methods. Accurately controlling the dopant implantation for an ultra-shallow junction is difficult with available ion implantation techniques and processes. When shallower implantations are attempted, implantation beam stability suffers as the implantation energy is decreased, which makes it more difficult to accurately aim and regulate the ion implant beam. Lateral deflections and additional penetration from the source/drain target area and depth using current implantation methods are generally on the order of 1000 xc3x85 in dimension.
As mentioned, the junctions are formed, in NMOS devices, by placing n-type regions in a p-type well such that the n-type regions are adjacent the gate structure. These defects, particularly the lateral deflections, result in n-type dopants coming to rest in the lightly p-type doped region under the gate. The presence of n-type carriers under the gate region increases parasitic capacitance between the gate and the source and drains and can increase the magnitude of leakage current. Source/gate and drain/gate parasitic capacitance requires additional current to overcome and thus slow the time response of the NMOS and circuits employing it. Higher leakage currents increase undesirable power drain by allowing current to flow when the NMOS is supposed to be xe2x80x9coffxe2x80x9d. Excessively high leakage currents can approach the xe2x80x9conxe2x80x9d state current levels and render the device useless as a switch/amplifier.
In addition to the above mentioned problems, ion implantation physically shoots ions into the silicon crystalline wafer, which damages the crystalline structure. The damage to the crystalline structure can result in increased leakage currents and parasitic capacitance. Typically, a subsequent annealing process is required to repair the crystalline damage following implantation. However, a subsequent anneal step adds complexity and cost to the fabrication process and can also result in unwanted diffusion of species in other regions of the semiconductor device.
It can be appreciated that there is an ongoing need in the field for a reliable, cost-effective method of creating reliable ultra-shallow source/drain junctions. The method should result in minimal parasitic capacitances and low leakage currents. It would be an advantage to employ a process that does not damage the crystal structure and thus require subsequent repair steps. It would be a further advantage for the method to simultaneously include other requisite fabrication processes, such as forming ohmic contacts to the active regions of the device.
The aforementioned needs are satisfied by the process for forming shallow source/drain junctions in a semiconductor substrate of the present invention. In one aspect, the process comprises forming a doped metallic layer on a first surface of the semiconductor substrate adjacent a region of the substrate that is to receive the source/drain region. The process also includes transforming the doped metallic layer into a low resistance contact layer adjacent the region of the substrate that is to receive the source drain region and inducing the dopant within the doped metallic layer to diffuse into the semiconductor substrate so as to form the source/drain region.
As the dopant within the doped metallic layer is diffused into the substrate, the problems associated with implantation are generally avoided. In one embodiment, the diffusion of the dopant occurs as a result of an anneal process that results in the dopant traveling into the substrate in a controlled fashion to a desired depth with less crystalline damage to the substrate. In one aspect, the diffusion of the dopant occurs at the same time as the transformation of the doped metallic layer into a low resistance contact layer and, in one embodiment, the diffusion and the transformation occurs as a result of annealing the doped metallic layer.
In another aspect of the invention, a diffusion control layer is formed on the doped metallic layer and the control layer is selected so that it interacts with the doped metallic layer during transformation of the doped metallic layer into the low resistance contact layer so as to limit the resulting thickness of the low resistance contact layer. In this way, a shallow source/drain junction can be formed and the diffusion of the low resistance contact layer into the semiconductor wafer can be more readily controlled.
In one embodiment, forming a doped metallic layer comprises first sputtering a layer of elemental near-noble metal, such as cobalt (Co) or nickel (Ni). Then, a layer of Co or Ni is electrodeposited or deposited in an electroless process along with no more than 10% dopant such as phosphorus (P). Thus the doped metallic layer comprises co-deposited Co(P) or Ni(P) with the P concentration no more than 10 atomic percent. The initial sputtering of the elemental Co or Ni acts as a seed for the subsequent co-deposition process. This helps to insure complete step coverage around the boundaries of the source and drain regions during the co-deposition.
In this embodiment, transforming the doped metallic layer comprises exposing the silicon substrate and associated structures to a rapid thermal processing. The RTP causes the Co or Ni doped metallic layer that is adjacent exposed regions of the substrate at the source and drain regions to form a salicide with the exposed silicon while simultaneously trapping the P dopant. Thus, a Co(Si) or Ni(Si) is formed above the source and drain regions with dopant (P) trapped within the salicide. The salicide has a work function intermediate to a metalization material and the doped silicon of the source/drain and thus forms a low resistance, ohmic contact to the active source and drain regions in a subsequent metalization process.
In this embodiment, inducing the diffusion of the dopant into the substrate occurs with dopant atoms contained within the grown salicide structures adjacent the source and drain regions. Inducing the diffusion comprises exposing the substrate and associated structures to the elevated temperatures of an anneal which induces the dopant atoms to thermally migrate into the silicon substrate along an error function gradient. Diffusing the dopant into the substrate offers the advantage that the junction depth is controlled by the anneal parameters and the constituency of the doped salicide and is not subject to the high minimum implant depth restrictions that are imposed on an ion implantation process. In addition, the diffusion process of the present invention incurs significantly less crystalline damage than a typical ion implant. Thus, a subsequent crystal repair step is not needed.
In this embodiment, the method includes forming a control layer atop the doped metallic layer, which comprises a layer of elemental titanium (Ti). The control layer of titanium is placed atop the doped metallic layer before transforming the doped metallic layer into a low resistance contact and inducing the dopant to diffuse into the semiconductor substrate. The control layer, titanium in this embodiment, partially alloys with the metal component of the doped metallic layer, Co or Ni. This Ti and Co or Ni alloy is resistant to silicidification and thus limits the thickness of the low resistant contact layer that is formed in a subsequent step. Limiting the thickness of the low resistance contact layer is desirable because a thinner contact layer will have a lower resistance than a thicker layer of the same composition.